After many months of development, a new version of WinUAE has been released. Version 4.10 brings now 100% cycle accuracy for the 68000-based unexpanded configuration. Also, initially planned for this release, the pixel-perfect OCS and ESC Denise mid-screen resolution was pushed for the upcoming 5.0 release.
Here are the details:
New hardware emulation features and update
- 68000 emulation is finally fully cycle accurate, last missing part, interrupt level change detection timing, is now cycle accurate.
- Custom chipset interrupt timing is now cycle accurate.
- CIA emulation is now fully cycle accurate. Timers were accurate previously but now also interrupt timing, TOD counting, CPU/E-clock sync, and more, including undocumented side-effects are cycle accurate.
- Serial port internal timing, interrupt timing, including SERDATR status bits are now cycle accurate (I used serial port interrupts as a timer in my cputester real 68000 interrupt timing tests)
- Audio interrupt timing is now cycle accurate (Was almost fully accurate previously).
- Blitter timing is now cycle accurate (previously startup behavior and interrupt timing was not fully accurate).
- Blitter line mode with invalid settings (for example width not 2, octant and line direction mismatch etc) is now almost accurately emulated. Some conditions are not fully correct.
- Copper is now cycle accurate, previously some special cases were not handled correctly.
- More undocumented chipset features implemented.
- A1000 Denise bug emulated: sprites end horizontally 1 lores pixel later than bitplane horizontal window end. Currently enabled when A1000 Agnus is selected.
- OCS/ECS vs AGA EHB on/off mid screen change different behavior emulated.
- Emulated chipset mode display is blanked if programmed mode is active but has invalid configuration (for example too short or too long sync pulses or missing syncs, genlock sync enabled without genlock, etc).
- Optional display mode change resync black screen delay.
- Programmed custom chipset modes again use also blanking timing to position the display in addition to vsync and hsync (Most real world SVGA monitors do the same).
- Max allowed programmed mode non-interlaced vertical line count is now 800 (increased from 592), special 700+ line programmed modes are possible and compatible with real SVGA monitors.
- Refresh cycles conflicting with bitplane DMA is now accurately emulated, including all display and audio related glitches it can cause.
- Optional Chip RAM and Slow RAM power up pattern emulation, enabled by default.
- Color palette is now filled with pseudo-random contents at power up (was all black previously).
- Monitor type selection. Composite sync or H/V sync. ECS Agnus/AGA programmed display modes can generate different C-Sync and H/V sync signals.
Link: